In a multiprocessor system, there is typically a system bus that provides communication among a plurality of system resources. One of the system resources may be a local processor with a cache controller and cache in combination with a local store. When a write from another system resource to the local store occurs, the cache controller must be notified so that it can invalidate the validity codes for data in the cache corresponding to the write address to the local store.
The local store can be accessed across the system bus by other resources in the system, or by the local processor itself. Further, the local processor may generate requests for access to system resources across the system bus. A deadlock occurs when the local processor attempts to use the system bus while the system bus is attempting to access the local store.
Significant processors in the data processing industry, such as Intel's 80386, do not support bus cycle retry. Thus, once a bus cycle is started, such as an attempt to use system resources, that cycle must run its course. Therefore, if the processor generates a system access request that becomes deadlocked, it will continue in a wait state until the deadlock is resolved.
Further, important cache controllers in the industry, such as Intel's 82385, prevent invalidating of validity bits in the cache unless the local bus is relinquished. However, the local bus will not be relinquished until the deadlocked system access request is satisfied.
Accordingly, there is a need for a method and apparatus for resolving deadlocks in data processing systems of this type.